Modern computer systems usually feature powerful digital processor integrated circuit devices. The processors are used to execute software instructions to implement complex functions, such as, for example, 3-D graphics applications, voice recognition, data visualization, and the like. Generally, the processors are configured with many different arrangements of memory, and other types of support or peripherals devices, on printed circuit boards. The specific configuration of processor, memory, peripheral device, etc. is usually dictated by the specific application of the overall device. Each configuration generally uses a printed circuit board, or motherboard, in order to interconnect the various components of the device.
As known by those skilled in the art, a printed circuit board (PCB) generally comprises a flat board that holds chips and other electronic components. The board is made of a plurality of layers that interconnect components via copper pathways.
Generally, PCBs are fabricated as an etched circuit on a fiberglass or plastic base. For example, a copper foil is placed over the base and covered with a photoresist. Light is shined through a negative image of the circuit paths onto the photoresist, hardening the areas that will remain after etching. After etching, the unhardened areas are washed away, leaving the circuit paths. The base is then finished (e.g., prepared for soldering, silk-screening, etc.) and the various integrated circuit components mounted.
As the complexity of integrated circuit technology has increased, the sophistication and complexity of PCB technology has also increased. For example, while the PCB of the 1970s connected discrete components together, more recent PCBs are used to interconnect chips, each containing millions of elementary components. Such highly integrated chips often have several hundred signal pins which must be interconnected with the other components of the PCB. Each of the signal interconnects have associated tolerances which define the manner in which they can be placed on the PCB in order to minimize the effects of, for example, crosstalk, EMI (electromagnetic interference) emissions, capacitance, signal skew, and the like. Because of these constraints, the PCB area for routing the signal traces (e.g., the conductor lines on the PCB which interconnect the signal pins of the components) is a valuable resource.
One prior art method of increasing the PCB area available for the signal interconnect, or trace, routing is to combine multiple boards, each having one or more trace conductor patterns, into a single multilayer PCB. This is achieved by gluing (laminating) several double-sided boards together with insulating layers in between. The number of layers is referred to as the number of separate trace conductor patterns. Most mother boards have between 4 and 8 layers, but PCBs with almost 100 layers have been made. The large number of layers facilitate or enable the fan out and routing of a large number of signal traces for a correspondingly large number of integrated circuit components.
A problem exists however, in the use of multilayer PCBs. Since each layer is fabricated using a separate etching process, each added layer adds to the expense of the overall PCB. Additionally, since each layer must be glued or otherwise combined with the other layers, the process of combining the layers adds to the expense and also increases the chances of introducing flaws into the finished PCB.
Another problem exists in the fact that interconnections between the layers of a PCB are implemented using “vias” which penetrate the trace conductor patterns of one layer to form a connection with the trace conductor patterns of another layer. Such vias waste space that could otherwise be used to route other signal traces. This can be particularly problematic in the case of a complex integrated circuit component having several hundred signal traces which must be routed. For example, where a microprocessor chip has a surface mount array of connections for 500 or more signal traces, such a chip forces designers to implement PCBs having many layers (e.g., four or more) simply to allow the signal traces from the inside of the ball surface mount array to escape past the signal traces on the outside of the array.
The traditional disposition of vias across a PCB is a dominant obstruction that can consume PCB real estate for trace routing. The placement of vias is ‘expensive’ in terms of trace routing since it consumes space that would otherwise be used for routing 4, 5, or even 6 traces. This problem exists for each layer of the PCB through which vias must be implemented. A designer's ability to cope with this problem is limited by conventional PCB fabrication design rules and via construction technology (e.g., which allocates a standard spacing per via, etc.).
Because of these reasons, conventional prior art routing limitations dictate that vias are regularly placed at the same pitch as their connecting ball. In other words, generally, only a minimal number of traces (e.g., one) can be routed between the vias. Every line (or row) of vias, in addition to the outer 2 rows requiring vias, requires a dedicated escape routing layer.
In addition to the problem of stifling the space to route the signal traces out from a surface mount array (typically of pins, but also any form of surface mount connection) to surrounding devices, the vias also have a severe impact on the layers in the PCB construction that are used to deliver the power into the IC. These layers (referred to as planes) not only carry power but also provide a path for transmission line return currents flowing between the IC and another device. The degradation of this copper plane caused by holes around the vias, limits how much power can be delivered and how fast the high-speed signals can transition.
For any form of PCB requiring a surface mount array pattern of connections consisting of many (e.g., 5, 6, or more) rows, what is required is a solution that can reduce the number of PCB layers required to implement interconnections for complex integrated circuit components. What is required is a solution that minimizes the impact of vias between layers of the PCB on the trace routing of the PCB. Additionally, what is required is a solution capable of functioning with conventional design rules and via construction technology for the fabrication of PCBs. The present invention provides a novel solution to the above requirements.